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|Designer||Damjan Lampret, with contributions from others in the OpenRISC community|
|Endianness||Big (unimplemented stub for Little)|
|General purpose||16 or 32|
OpenRISC is a project to develop a series of open source instruction set architectures based on established reduced instruction set computing (RISC) principles. It is the original flagship project of the OpenCores community.
The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support, and the OpenRISC 1200 implementation of this was designed by Damjan Lampret in 2000, written in the Verilog hardware description language.
A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups have demonstrated ORPSoC and other OR1200 based designs running on FPGAs, and there have been a number of commercial derivatives produced.
The instruction set is a reasonably simple MIPS-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32 and 64 bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop/server processors: a supervisor mode and virtual memory system, optional read, write and execute control for memory pages, and instructions for synchronization and interrupt handling between multiple processors.
Another notable feature is a rich set of SIMD instructions intended for digital signal processing.
Most implementations are on FPGAs which give the possibility to iterate on the design at the cost of performance.
As the OpenRISC 1000 is now considered stable, ORSoC (owner of OpenCores) launched a crowd-funding project trying to build a cost-efficient ASIC to get improved performance. ORSoC faced criticism for this from the community. The project never reached the goal.
As of April 2017, no open-source ASIC has been produced yet.
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14 and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12. Flex and Jennic Limited manufactured the OpenRISC as part of an ASIC. Samsung use the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series). Allwinner Technology are reported to use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC.
TechEdSat, the first NASA OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.
The OpenRISC community have ported the GNU toolchain to OpenRISC to support development in C and C++. Using this toolchain the newlib, uClibc, musl (as of release 1.1.4) and glibc libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical development environment based on this toolchain. A project to port LLVM to the OpenRISC 1000 architecture started in early 2012 (project page).
The OR1K project provides an instruction set simulator, or1ksim. The flagship implementation, the OR1200, is a register-transfer level (RTL) model in Verilog HDL, from which a SystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative set up by Imperas.
The mainline Linux kernel gained support for OpenRISC in version 3.1. The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k). Previously OpenRISC 1000 architecture, but this has now been superseded by the mainline port.