Advanced Encryption Standard instruction set is now integrated in to many processors. The purpose of the instruction set is to improve the speed, as well as the resistance to side-channel attacks, of applications performing encryption and decryption using Advanced Encryption Standard (AES). They are often implemented as instructions implementing a single round of AES along with a special version for the last round which has a slightly different method.
x86 architecture processors
AES-NI (or the Intel
Advanced Encryption Standard New Instructions; AES-NI) was the first major implementation. AES-NI is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.
Intel processors support the AES-NI instruction set:
Westmere based processors, specifically:
Sandy Bridge processors:
Desktop: all except Pentium, Celeron, Core i3.
  Mobile: all Core i7 and Core i5. Several vendors have shipped BIOS configurations with the extension disabled; a BIOS update is required to enable them.  
Ivy Bridge processors.
All i5, i7, Xeon and i3-2115C only. 
Haswell processors (all except i3-4000m, Pentium and Celeron). 
Broadwell processors (all except Pentium and Celeron).
Silvermont/Airmont processors (all except Bay Trail-D and Bay Trail-M).
Kaby Lake processors. Coffee Lake processors.
AMD processors support AES instructions:
Puma-based processors and newer "Heavy Equipment" processors
Zen based processors Zen+ based processors
Hardware acceleration in other architectures
AES support with unprivileged processor instructions is also available in the latest
SPARC processors ( T3, T4, T5, M5, and forward) and in latest ARM processors. The SPARC T4 processor, introduced in 2011, has user-level instructions implementing AES rounds. These instructions are in addition to higher level encryption commands. The  ARMv8-A processor architecture, announced in 2011, including the ARM Cortex-A53 and A57 (but not previous v7 processors like the Cortex A5, 7, 8, 9, 11, 15 ) also have user-level instructions which implement AES rounds. In August 2012,  IBM announced that the then-forthcoming  Power7+ architecture would have AES support. The commands in these architectures are not directly compatible with the AES-NI commands, but implement similar functionality.
IBM z9 or later mainframe processors support AES as single-opcode (KM, KMC) AES ECB/CBC instructions via IBM's CryptoExpress hardware
These single-instruction AES versions are therefore easier to use than Intel NI ones, but may not be extended to implement other algorithms based on AES round functions (such as the  Whirlpool hash function).
Supporting x86 CPUs VIA x86 CPUs, AMD Geode, and Marvell Kirkwood (ARM, mv_cesa in Linux) use driver-based accelerated AES handling instead. (See Crypto API (Linux).)
The following chips, while supporting AES hardware acceleration, do not support an AES instruction set:
Programming information is available in
ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
ARM cryptographic extensions optionally supported on ARM Cortex-A30/50/70 cores
Cryptographic hardware accelerators/engines
Atmel XMEGA (on-chip accelerator with parallel execution, not an instruction) 
SPARC T3 and later processors have hardware support for several crypto algorithms, including AES. Cavium Octeon MIPS All Cavium Octeon MIPS-based processors have hardware support for several crypto algorithms, including AES using special coprocessor 3 instructions. 
AES-NI Performance Analyzed, Patrick Schmid and Achim Roos found "impressive results from a handful of applications already optimized to take advantage of Intel's AES-NI capability". A performance analysis using the  Crypto++ security library showed an increase in throughput from approximately 28.0 cycles per byte to 3.5 cycles per byte with AES/ GCM versus a Pentium 4 with no acceleration. 
Most modern compilers can emit AES instructions.
Much security and cryptography software supports the AES instruction set, including the following core infrastructure:
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